1. Technical Field
The present invention belongs to the technical field of semiconductor devices and specifically relates to a tunneling field effect transistor (TFET) and a manufacturing method thereof.
2. Description of Related Art
The conventional metal-oxide-semiconductor transistor (MOS transistor), as shown in FIG. 1, including the following steps: firstly, form a dielectric gate layer 104 and a gate 105 usually formed of heavily-doped polycrystalline silicon on a substrate 101, and then form a source region 102 and a drain region 103 through the ion implantation method. After forming the source region and drain region by the ion implantation method, high-temperature (about 1000) annealing is required to activate the doping, so as to eliminate the lattice damage caused by ion implantation and reduce contact resistance. However, the processing at such high temperature will cause the secondary doping (boron or phosphorus) diffusion of the source region and drain region, which results in the change of the junction depth and channel length, and ultimately causes the device performance to deviate from the design standard. In particular, as the device characteristic dimension is reduced to below the technology node of 50 nanometers, the junction depth and channel length of the source region and drain region all enter the nanometer magnitude, while the ultra shallow junction of the source region and drain region cannot be realized through regular methods, which poses huge challenge to the processing of small-size devices. In addition, in order to overcome the short-channel effect of the MOS tube, TFET has been proposed and studied.
In recent years, since they are of the ideal system of physical and chemical properties determined by size and dimension, one-dimension nanometer structures, such as nanotubes, nanowires and nanobelts, have triggered wide research interest. Based on its unique physical and chemical properties, interests in one-dimensional semiconductor nanowire has gradually increased, and it is believed to be the possible basic component of integrated circuits in the future. Due to its properties similar to semiconductors, metallic oxide ZnO semiconductor nanowire has attracted wide attention. However, because of its inconvenient manufacturing, no method has been proposed to conduct convenient and large-scale array production. Moreover, it is also difficult to process it into planar device channels. Therefore, it is still a huge challenge to integrate ZnO nanowire into TFET as the channel.